Understanding Loop Timing (FPGA Interface)

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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The following modules have an internal master timebase and are internally timed:

  • NI 9202
  • NI 9225
  • NI 9227
  • NI 9229
  • NI 9230
  • NI 9231
  • NI 9232
  • NI 9234
  • NI 9235
  • NI 9236
  • NI 9237
  • NI 9238
  • NI 9239
  • NI 9242
  • NI 9244
  • NI 9246
  • NI 9247
  • NI 9250
  • NI 9251
  • NI 9260
  • NI 9770
  • NI 9775

Do not use the Loop Timer or Wait functions in a loop with an FPGA I/O Node that acquires data from one of these modules.

When you create a loop that reads data from one of these modules, make sure the loop does not execute slower than the data rate of the module. If the loop execution time is slower than the data rate, the FPGA I/O Node returns an overrun warning and continues to read data. The overrun warning means that the data the FPGA I/O Node returns is valid, but the function missed one or more data points since the last time it read data from the module. The function returns the overrun warning when all of the following conditions are true:

  • The module is in acquisition mode.
  • An FPGA I/O Node that is acquiring data from the module executes at least once after you put the module in acquisition mode.
  • The FPGA I/O Node did not read one or more data points since the previous time the function executed.

If the application acquires multiple buffers of data from the module and the timing relationship between them is not important, you can ignore the overrun warning returned with the first point of each buffer.

Avoiding Overrun Warnings

To avoid overrun warnings, develop the FPGA VI to meet the following guidelines:

Conditions Guidelines
Your application acquires multiple buffers of data from a module with an internal master timebase. If the timing relationship between the buffers is not important, you can ignore the overrun warning returned with the first point of each buffer.
You are reading from multiple modules with an internal master timebase in the same loop.
  • Use one FPGA I/O Node to read the channels.
  • Configure the modules to share a master timebase source and have the same data rate.
You are reading from a module with an internal master timebase and another analog input module in the same loop.
  • If the rate at which you can acquire data from the other module is as fast or faster than the data rate configured for the module with an internal master timebase, you can read from both modules in the same loop.
  • If you use the same FPGA I/O Node to read data from all modules, the FPGA I/O Node does not return data for the other module until the module with an internal master timebase acquires data.
  • If the other module has a slower data rate than the module with an internal master timebase and you read from both modules in the same loop, the FPGA I/O Node for the module with an internal master timebase returns an overrun warning and continues reading data. To avoid missing data, you can either change the data rate of the module with an internal master timebase or read from each module in a different loop.

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