NI 9218 (FPGA Interface)

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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CompactRIO 2-Channel, 24-Bit Dynamic Universal Analog Input Module

FPGA I/O Node

You can use an FPGA I/O Node, configured for reading, with this device.

Note  You can synchronize an NI 9218 module with other modules that have a selectable timebase source.

Terminals in Software

Use the FPGA I/O Node to access the following terminals for this device.

Terminal Description
AIx channel x, where x is the number of the channel. The NI 9218 has channels 0 to 1.
Onboard Clock Gives access to the onboard clock in the LabVIEW block diagram. The Onboard Clock frequency is 13.1072 MHz. Use the FPGA I/O Node in a single-cycle Timed Loop to access this channel. You must export the Onboard Clock of the NI 9218 to access this channel.
Start Channel that controls when the NI 9218 starts acquiring data. If TRUE is written to the Start channel, the NI 9218 starts acquiring data. When the NI 9218 is acquiring data, you must write TRUE to the Stop channel before you can access properties for the module. If FALSE is written to the Start channel, no operation is performed.
Stop Channel that controls when the NI 9218 stops acquiring data. If TRUE is written to the Stop channel, the NI 9218 stops acquiring data. When the NI 9218 is acquiring data, you must write TRUE to the Stop channel before you can access properties for the module. If FALSE is written to the Stop channel, no operation is performed.

You can read TEDS information from the NI 9218.

Arbitration

This device supports only the Arbitrate if Multiple Requestors Only option for arbitration. You cannot configure arbitration settings for this device.

Module Methods

Use the FPGA I/O Method Node to access the following module method for this device.

Method Description
Check Cached Status Returns Booleans for each channel that indicate whether there was an excitation fault or open loop on the channel since the last execution of the Check Cached Status method. When the FPGA I/O Node reads the channels, the FPGA VI determines the state of the channels and caches any TRUE value until the Check Cached Status method executes.
  • Excitation Fault—Returns an array of Boolean values. A value of TRUE in any index indicates that the channel sharing a number with that index detected an excitation fault on the channel at some point after the last time that the Check Cached Status method executed.
  • Open Loop—Returns an array of Boolean values. A value of TRUE in any index indicates that the channel sharing a number with that index detected an open loop on the channel at some point after the last time that the Check Cached Status method executed.

I/O Properties

Use the FPGA I/O Property Node to access the following I/O properties for this device.

Property Description
Input Configuration Sets the input configuration of the corresponding channel to one of ten modes: ±60 V; ±16 V; ±16 V, 12 V Ex.; ±65 mV; ±65 mV, 12 V Ex.; ±20 mA; ±20 mA, 12 V Ex.; ±22 mV/V Bridge, 2 V Ex.; ±22 mV/V Bridge, 3.3 V Ex.; ±5 V IEPE AC Coupled.
LSB Weight (±16 V range) Returns the LSB weight in pV/LSB for the ±16 V range.
LSB Weight (±20 mA range) Returns the LSB weight in fV/LSB for the ±20 mA range.
LSB Weight (±22 mV/V range) Returns the LSB weight in fV/LSB for the ±22 mV/V range.
LSB Weight (±5 V IEPE range) Returns the LSB weight in pV/LSB for the ±5 V IEPE range.
LSB Weight (±65 mV range) Returns the LSB weight in fV/LSB for the ±65 mV range.
LSB Weight (±60 V range) Returns the LSB weight in pV/LSB for the ±60 V range.
Offset (±16 V range) Returns the calibration offset in nV for the ±16 V range.
Offset (±20 mA range) Returns the calibration offset in nV for the ±20 mA range.
Offset (±22 mV/V range) Returns the calibration offset in nV for the ±22 mV/V range.
Offset (±5 V IEPE range) Returns the calibration offset in nV for the ±5 V IEPE range.
Offset (±65 mV range) Returns the calibration offset in nV for the ±65 mV range.
Offset (±60 V range) Returns the calibration offset in nV for the ±60 V range.
Offset Cal Enable Enables offset calibration. This disconnects both signal input pins and internally connects a short to the ADC driver circuitry.
Shunt Cal Enable Controls the shunt calibration switch for each channel.

Module Properties

Use the FPGA I/O Property Node to access the following module properties for this device.

Property Description
Data Rate Sets the rate at which the NI 9218 acquires data.
Module ID Returns the module ID, 0x7757.
Serial Number Returns the unique serial number of the module.
Vendor ID Returns the NI vendor ID, 0x1093.

Excitation Protection

The NI 9218 excitation circuit is protected from overcurrent and overvoltage fault conditions. A fault condition also occurs if the voltage supplied to the external power connector on the NI 9218 is below the minimum required voltage, if the excitation pins on the NI 9218 are shorted together, or if the connected load exceeds the powered sensor output current limit. The circuit is automatically disabled in the event of a fault condition. Whenever possible, a channel automatically recovers after the fault is removed.

You must wire error terminals on the FPGA I/O Property Nodes to receive notification of overcurrent and overvoltage faults. LabVIEW returns error 65654 if there is an overcurrent or overvoltage fault on at least one channel. If a warning occurs, only the channel(s) with the fault are affected and all other channels on the module continue to function properly without interruption. If an error occurs, the module is unable to recover from the fault condition and you must restart the module after the fault is removed.

Single-Cycle Timed Loop

This device does not support the single-cycle Timed Loop.

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