NI 9402 (FPGA Interface)

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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CompactRIO 4-Channel, LVTTL Digital Input/Output Module

FPGA I/O Node

You can use an FPGA I/O Node, configured for reading and writing, with this device.

Terminals in Software

Use the FPGA I/O Node to access the following terminals for this device.

Terminal Description
DIOx Digital input/output channel x, where x is the number of the channel. The NI 9402 has DIO channels 0 to 3.
DIO3:0 Digital port consisting of channels 0 through 3. Channel 3 is returned in the MSB, and channel 0 is returned in the LSB.

Arbitration

You can configure the arbitration settings for digital output channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate. Digital input channels of this device support only the Never Arbitrate option for arbitration. You cannot configure arbitration settings for the digital input channels of this device.

I/O Methods

Use the FPGA I/O Method Node to access the following I/O methods for this device.

Method Description
Set Output Data Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method.
Set Output Enable Sets the line direction of the digital channel or the DIO3:0 digital port. Refer to the FPGA I/O Method Node (FPGA Module) topic for more information on this method.
Wait on Any Edge Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Any Edge method waits for the next falling or rising edge. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Falling Edge Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Falling Edge method waits for the next falling edge. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on High Level Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input specifies in FPGA clock ticks how long the Wait on High Level method waits for the next high level. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Low Level Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input specifies in FPGA clock ticks how long the Wait on Low Level method waits for the next low level. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Rising Edge Pauses the execution of the I/O Method Node until the next rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Rising Edge method waits for the next rising edge. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.

Module Method

Use the FPGA I/O Method Node to access the following module method for this device.

Method Description
Check Status Returns a Boolean value that indicates whether the module is ready.
Note  During the first 2 seconds after you reset the FPGA VI, the error terminals on this method may not correctly report certain types of errors.

I/O Properties

This device does not support any I/O properties.

Module Properties

Use the FPGA I/O Property Node to access the following module properties for this device.

Property Description
Module ID Returns the module ID.
Serial Number Returns the unique serial number of the module.
Vendor ID Returns the NI vendor ID, 0x1093.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop. Configure the number of input synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Node Properties dialog box. Configure the number of output synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box.

The NI 9402 supports the following output synchronizing register options:

  • Number of Synchronizing Registers for Output Data when used in SCTL
  • Number of Synchronizing Registers for Output Enable when used in SCTL

These two options support the same functionality as the Number of Synchronizing Registers for Output Data and Number of Synchronizing Registers for Output Enable options described in the Advanced Code Generation FPGA I/O Properties Page (FPGA Module) topic, with the exception that you can use these options only in a single-cycle Timed Loop. You can implement either 0 or 1 synchronizing registers inside the single-cycle Timed Loop, however, if you configure 0 synchronizing registers outside of the single-cycle Timed Loop, the FPGA VI implements 1 synchronizing register by default.

When the module is within a single-cycle Timed Loop, it must be ready to perform digital I/O before a loop containing digital I/O starts. Poll the Ready output of the Check Status method to determine whether the module is ready. Digital input operations return invalid data if the module is not ready. The module also might ignore or delay digital output operations if it is not ready.

While the module is performing digital I/O within a single-cycle Timed Loop, do not perform property reads or remove the module from the chassis. Doing any of these actions causes the module to be unable to perform digital I/O and the Ready output of the Check Status method to return FALSE.

FPGA Target Clock Support

This device supports only top-level FPGA target clock rates and single-cycle Timed Loop clock rates that are multiples of 40 MHz, such as 40 MHz, 80 MHz, 120 MHz, and so on.

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