NI 9472 (FPGA Interface)

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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CompactRIO 8-Channel, 24 V, Sourcing Digital Output Module

FPGA I/O Node

You can use an FPGA I/O Node, configured for writing, with this device.

Terminals in Software

Use the FPGA I/O Node to access the following terminals for this device.

Terminal Description
DOx Digital output channel x, where x is the number of the channel. The NI 9472 has DO channels 0 to 7.
DO7:0 Digital port consisting of channels 0 through 7. Channel 7 is returned in the MSB, and channel 0 is returned in the LSB.

Arbitration

You can configure the arbitration settings for the channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.

I/O Methods

This device does not support any I/O methods.

Module Methods

Use the FPGA I/O Method Node to access the following module method for this device.

Method Description
Check Status Returns a Boolean value that indicates whether the module is ready.
Note  During the first 2 seconds after you reset the FPGA VI, the error terminals on this method may not correctly report certain types of errors.

I/O Properties

This device does not support any I/O properties.

Module Properties

Use the FPGA I/O Property Node to access the following module properties for this device.

Property Description
Module ID Returns the module ID.
Serial Number Returns the unique serial number of the module.
Vendor ID Returns the NI vendor ID, 0x1093.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop. Configure the number of output synchronizing registers for the channels of this device in the Advanced Configuration dialog box.

When the module is within a single-cycle Timed Loop, it must be ready to perform digital output before a loop containing digital output starts. Poll the Ready output of the Check Status method to determine whether the module is ready. The module might ignore or delay digital output operations if it is not ready.

While the module is performing digital output within a single-cycle Timed Loop, do not perform property reads or remove the module from the chassis. Doing either of these actions causes the module to be unable to perform digital output and the Ready output of the Check Status method to return FALSE.

FPGA Target Clock Support

This device supports only top-level FPGA target clock rates and single-cycle Timed Loop clock rates that are multiples of 40 MHz, such as 40 MHz, 80 MHz, 120 MHz, and so on.

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