Synchronizing Multiple Modules (FPGA Interface)

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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You can synchronize multiple modules that are connected to the same FPGA device if your application meets the following requirements:

  • The modules must use the same master timebase source
  • The modules must start acquisition mode at the same time
  • A single FPGA I/O Node function must read the synchronous data

You must create FPGA I/O items for the module before you can configure the items using the FPGA I/O Node. Develop the FPGA VI to meet the guidelines described in the following table.

For delta-sigma modules, you will need to synchronize multiple sample rates.

Guideline Details
Share a master timebase source Configure the modules to share master timebase source.
Start the synchronized acquisition
  • Configure an FPGA I/O Node with Start channels for the module you want to synchronize.
  • Wire a Boolean constant set to TRUE to each Start channel.
  • Ensure that all I/O channels are in the same FPGA I/O Node. Otherwise, the FPGA I/O Node will not return synchronized data.
Acquire data from synchronized modules with the same data rate
  • Configure an FPGA I/O Node with all of the channels from which you want to synchronously sample.
  • Ensure that all I/O channels are in the same FPGA I/O Node. Otherwise, the FPGA I/O Node will not return synchronized data.
  • Refer to the Synchronizing NI 923x Modules (FPGA) VI in labview\examples\CompactRIO\Module Specific\NI 923x\Synchronizing NI 923x Modules\Synchronizing NI 923x Modules.lvproj for an example of synchronizing multiple modules with the same data rate.
Acquire data from synchronized modules with different data rates
  • If you synchronize modules that are configured for different data rates, create a separate loop for each data rate in the FPGA VI.
  • In each loop, configure an FPGA I/O Node with all of the channels that are configured for the data rate of that loop. If you place channels that are configured for different rates in the same loop, LabVIEW returns an overrun warning, error 65539, from the FPGA I/O Node when you run the VI.
  • A delay occurs before the FPGA I/O Node returns the first data point. The length of the delay depends on the data rate and model number of the module. The equation for the delay is provided in the following table.
Understand the maximum sample rate when synchronizing multiple modules

Equation for synchronizing multiple samples rates
Module Decimation Rate, m Clock Divider, n Time to First Sample (s)
NI 9250, NI 9251 32 n = 1 (281.625 * m * n + 5.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
64 n = 1 (281.625 * m * n + 8.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
128, ..., 1,024 n = 1 (281.625 * m * n + 6.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
32, ..., 1,024 n = 2, ..., 12 (281.625 * m * n + 5.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
NI 9218, NI 9225, NI 9227, NI 9229, NI 9234, NI 9237, NI 9238, NI 9239, NI 9242, NI 9244, NI 9246, NI 9247 256 n = 1 (8.5 + n * 34,152) * Master_Timebase_Period
n = 2, ..., 31 (5.5 + n * 34,152) * Master_Timebase_Period
NI 9230, NI 9232 64 n = 1, ..., 31 77/Fs + 4-5 Master_Timebase_Period
128 n = 1, ..., 31 72/Fs + 4-5 Master_Timebase_Period
256 n = 1, ..., 31 68/Fs + 4-5 Master_Timebase_Period
NI 9231 64 n = 1 (281.625 * m * n + 8.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
128, ..., 1,024 n = 1 (281.625 * m * n + 6.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
64, ..., 1,024 n = 2, ..., 12 (281.625 * m * n + 5.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
NI 9235, NI 9236 512 n = 1, ..., 31 39/Fs + 110.5 MClk + 1 OClk + Analog Delay
Notes:
Master_Timebase_Period = period of the internal or external clock that the module uses (1/13.1072 MHz, 1/12.8 MHz, or 1/10 MHz).
Fs = sample rate.
The divider and decimation rate depend on which sample rate you select. The datasheet for each modules provides an equation to help you determine the clock divider and decimation rate and/or lists the clock divider and decimation rate for each sample rate.
  • For example, the NI 9232 Datasheet lists the decimation rate as 64 and clock divider as 1 when sampling at 102.4 kHz.
  • Using the equation in the NI 9218 Datasheet, we can determine that the clock divider is 1 when the sample rate is 51.2 kHz. n = Master_Timebase_Frequency/256/fs (this is the equation provided in the NI 9218 Datasheet reorganized to solve for n).

Equation for synchronizing multiple samples rates
Module Clock Divider, b Time to First Sample (s)
NI 9202 1 (5.40625 * a * b * c * d + 4.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
2, ..., 11 (5.40625 * a * b * c * d + 5.5) * Master_Timebase_Period ± 1 Master_Timebase_Period
Notes:
Master_Timebase_Period = period of the internal or external clock that the module uses (1/13.1072 MHz, 1/12.8 MHz, or 1/10 MHz).
a = ADC Decimation Rate
b = Timebase Clock Divider
c = ADC Clock Divider
d = Filter Decimation Rate
Refer to the NI 9202 Datasheet on ni.com for the values of a, b, c, and d for each sample rate.

Related Topics

Configuring the Master Timebase Source for a Module

Understanding the Maximum Sample Rate when Synchronizing Multiple Modules (FPGA Interface)

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