Creating Component-Level IP for the sbRIO-9651

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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Use the sbRIO CLIP Generator to generate a unique socketed CLIP that you can import into a LabVIEW project. The sbRIO CLIP Generator completes the following tasks for you:

  • Generates processor peripherals
  • Configures the raw FPGA I/O pins
  • Generates a LabVIEW FPGA I/O Node interface for the socketed CLIP

Complete the following steps to launch the sbRIO CLIP Generator and create a new CLIP.

  1. Create a new LabVIEW project.
  2. Add an FPGA target to the project. In the Add Targets and Devices dialog box, select Real-Time Single-Board RIO»sbRIO-9651.
  3. In the Project Explorer window, right-click the Chassis (sbRIO-9651) item and select New»FPGA Target.
  4. Right-click the FPGA Target item and select Launch sbRIO CLIP Generator.
    Note Note  You can also launch the sbRIO CLIP Generator outside of LabVIEW in the following ways:
    • (Windows 8.x) Click the NI Launcher tile on the Start screen and select CompactRIO»Single-Board RIO»sbRIO CLIP Generator.
    • (Windows 7 or earlier) Select Start»All Programs»NI»CompactRIO»Single-Board RIO»sbRIO CLIP Generator.
  5. Step through the pages of the sbRIO CLIP Generator to name the CLIP, configure the peripherals you want to enable, create a LabVIEW FPGA I/O Node interface for the CLIP, and configure clock resources for the CLIP.
    Tip Tip  Click Help in the sbRIO CLIP Generator or browse to the <NI>\CompactRIO\sbRIO\CLIP Generator directory to launch the NI Single-Board RIO CLIP Generator Help, which contains more information about using the sbRIO CLIP Generator.
    Note Note  If you want to make changes to an existing CLIP after it has been created, you must manually edit the generated CLIP files. You cannot use the sbRIO CLIP Generator to edit an existing CLIP. However, you can load the configuration for a previously saved CLIP so you can use it as the basis for a new CLIP.

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Adding a CLIP for the sbRIO-9651 to a LabVIEW Project

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Using VHDL Code as Component-Level IP (FPGA Module)


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