Getting Started with the sbRIO-9651 in LabVIEW

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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The sbRIO-9651 System on Module (SOM) requires a mated carrier board in order to function as a complete LabVIEW FPGA and LabVIEW Real-Time target. The sbRIO-9651 reserves some pins on its connector for specific functionality, such as primary Ethernet and USB ports, but provides several banks of additional pins that you can configure for purposes specific to your application.

The sbRIO-9651 SOM Development Kit includes a reference carrier board, which shows an example of how to implement additional I/O functionality you might require, such as Serial, CAN, and secondary Ethernet.

To use the sbRIO-9651 as a LabVIEW FPGA and LabVIEW Real-Time target in a LabVIEW project, you must first create a socketed component-level IP (CLIP) that defines the I/O configuration to use in your application.

Use this tutorial to create a CLIP for the sbRIO-9651 and add it to a LabVIEW project.

Before You Begin

  • Before you write any software, use the sbRIO-9651 System on Module Carrier Board Design Guide on to plan the layout of your carrier board and define the purpose of each pin on the connector. When you create a CLIP for the sbRIO-9651, you must already know the following details:
    • Which processor peripherals you want to enable
    • What pins you want to use
    • What I/O standards and drive strength you want to use for the pins
    • What I/O voltage level you require
    • What LabVIEW FPGA I/O Nodes your application will require
    • What timing constraints or clock resources you require

Get started: Get started

Creating Component-Level IP for the sbRIO-9651

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Using VHDL Code as Component-Level IP (FPGA Module)


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