sbRIO-9627 (FPGA Interface)

NI CompactRIO Device Drivers Help

Edition Date: December 2017

Part Number: 373197L-01

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Single-Board Reconfigurable I/O (MIO)

16 AI channels, 4 AO channels, 4 3.3 V DIO channels, 2 RS-232 Serial ports, 1 RS-485 Serial port, 1 CAN port, RIO mezzanine card connector, Zynq-7020 FPGA

FPGA I/O Node

You can use an FPGA I/O Node, configured for reading and writing, with this device.

Terminals in Software

Use the FPGA I/O Node to access the following terminals for this device.

Terminal Description
Connector0/AIx Analog input channel x, where x is the number of the channel. The sbRIO-9627 has AI channels 0 to 15.
Connector0/AOx Analog output channel x, where x is the number of the channel. The sbRIO-9627 has AO channels 0 to 3.
Connector0/DIOx Digital input/output channel x, where x is the number of the channel. The sbRIO-9627 has channels 0 to 3. Use the FPGA I/O Node or the Set Data Output or Set Data Enable method to access this channel.

Arbitration

You can configure the arbitration settings for the DIO channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.

I/O Methods

Use the FPGA I/O Method Node to access the following I/O methods for this device.

Method Description
Set Output Data Refer to the FPGA I/O Method Node topic for a description of this method.
Set Output Enable Refer to the FPGA I/O Method Node topic for a description of this method.

Module Methods

This device does not support any module methods.

Properties

Use the FPGA I/O Property Node to access the following properties for this device.

Property Description
Terminal Mode Sets the terminal mode for a channel as RSE (referenced single-ended) or DIFF (differential). This property overwrites the value you configure in the FPGA I/O Properties dialog box.
Voltage Range Sets the input range for a channel as ±10 V, ±5 V, ±2 V, or ±1 V. This property overwrites the value you configure in the FPGA I/O Properties dialog box.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop for digital I/O only. Configure the number of output synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. Configure the number of input synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Node Properties dialog box.

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