|LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes|
The NI 5170R/5171R has flexible clocking circuitry, which allows you to generate a 250 MHz clock locked to an internal or external Reference Clock or route an external clock as a source. The main clock sourced from this circuitry is the Sample Clock, which is used to clock the ADCs and the related FPGA and synchronization logic. To configure device clocks from the host, use the Configuration instrument design library.
The Sample Clock may either be generated from a 250 MHz phase-lock loop (PLL) locked to a user-selectable Reference Clock or from a user-provided external clock source connected to the AUX I/O CLK IN connector or to the PXIe_DStarA backplane signal. In the FPGA, the Data Clock is a clock source which is derived from the Sample Clock. The Data Clock runs at half the frequency of the Sample Clock. Because of this, two ADC samples per channel are provided to the FPGA for each cycle of the Data Clock.
This clock is routed to the ADCs, the FPGA, and the Time-to-Digital Conversion (TDC) circuits.
|Note When using an external Sample Clock, the performance of the instrument will be dependent on the quality of that clock source. For the requirements of the CLK IN terminal, refer to the device specifications.|
The Sample Clock may be phase locked to different reference sources. You may lock the PLL to an internal reference, to the PXIe_Clk10 signal from the backplane, or to an external reference that you provide on the AUX I/O CLK IN pin.
|Note When using an external Reference Clock, the performance of the instrument will be dependent on the quality of that clock source. For the requirements of the CLK IN terminal, refer to the device specifications.|
You can use the NI 5170R/5171R AUX I/O front panel connector to export the Reference Clock through the CLK OUT terminal. This signal will be exported using a 3.3V LVCMOS buffer.