Configuring Clock Resources for a CLIP

NI Single-Board RIO CLIP Generator Help

Edition Date: August 2015

Part Number: 375106C-01

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Complete the following steps to use the Clock Settings page of the sbRIO CLIP Generator to specify the pins to connect to LabVIEW FPGA clock lines and reserve additional clock resources in the CLIP for the NI sbRIO target. The sbRIO CLIP Generator will create the VHDL logic required to connect the pins to LabVIEW FPGA clock lines.

  1. From the Available Pins control, select a pin. The Clock Capability column specifies one of the following configurations for each pin:
    • None—The pin does not provide a direct connection to the clock distribution network on the FPGA.
    • Single-region—The pin provides a direct connection to the clock distribution network on a specific region, or bank of pins, on the FPGA.
    • Multi-region—The pin provides a direct connection to the clock distribution network on the entire FPGA.
  2. From the Clock Direction control, select one of the following options:
    • To CLIP—Exports a clock signal from LabVIEW FPGA to the CLIP.
    • From CLIP—Imports a clock signal from the CLIP to LabVIEW FPGA.
    Note Note  For best performance, National Instruments recommends that you configure From CLIP clocks to use pins with single- or multi-region clock capability, depending on how widely your CLIP design will use this clock in the FPGA. Select Multi-region if you are not sure which region to select. You can still configure a clock line for a pin that is not clock-capable, but the sbRIO CLIP Generator displays a warning icon for the clock to indicate that performance from this pin might diminish.
  3. Click Add. The LabVIEW Clocks table lists the created clock line.
  4. If you specified a From CLIP clock, you must configure the following options in the Clock Parameters section so that the LabVIEW FPGA Module can handle the clock signal correctly:
    • Frequency in MHz—The minimum and maximum frequencies the clock signal supports. If the clock signal has a fixed frequency, specify the same value for the minimum and maximum.
    • Duty Cycle—The minimum and maximum percentage of time the clock signal is high.
    • Accuracy in PPM—The amount, in parts per million (PPM), that the clock signal may deviate from its specified frequency under normal operating conditions.
    • Jitter in Picoseconds—The acceptable absolute difference, in picoseconds, between any one clock period and the average clock period. Jitter may also be called frequency stability.
    • Supports Derived Clocks—When you enable this option, the sbRIO CLIP Generator adds a Source Clock Ready signal and Derived Clocks Valid signal to the generated VHDL file for the CLIP.
  5. In the Additional Clock Resources Reserve section, configure the following options if your CLIP design will include any clock management resources from the FPGA.
    • MMCMs—The number of mixed-mode clock manager (MMCM) resources to reserve.
    • BUFGs—The number of global clock buffer (BUFG) resources to reserve.
    Note Note  Configuring these options reserves these resources, but you must manually edit the VHDL file to instantiate them. Refer to Xilinx documentation for more information about MMCMs and BUFGs and how to instantiate them in VHDL.
  6. Repeat the preceding steps to create additional clock lines for the CLIP. You can drag and drop created clock lines in the LabVIEW Clocks table.
  7. Click Next to continue to the CLIP Summary page.

Continue: Continue

Finishing the CLIP Design

Related Topics

Using CLIP Clocks in the LabVIEW Help (FPGA Module)

Example VHDL Code for CLIP Clocks in the LabVIEW Help (FPGA Module)

Using FPGA Clocks and Timing in the LabVIEW Help (FPGA Module)


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